PolarFire SoC M-Mode Support with SC QSPI Flash#667
PolarFire SoC M-Mode Support with SC QSPI Flash#667dgarske wants to merge 11 commits intowolfSSL:masterfrom
Conversation
dgarske
force-pushed
the
polarfire_soc_m
branch
from
eba460a to
c9486a9
Compare
dgarske
changed the title
dgarske
force-pushed
the
polarfire_soc_m
branch
from
c9486a9 to
acfd97b
Compare
dgarske
force-pushed
the
polarfire_soc_m
branch
from
63adfa7 to
dd0a6be
Compare
There was a problem hiding this comment.
Pull request overview
This PR adds Machine Mode (M-mode) support for PolarFire SoC MPFS250T, enabling wolfBoot to run directly from eNVM without requiring HSS (Hart Software Services) or DDR. The implementation boots from eNVM, executes from L2 Scratchpad SRAM, and loads signed applications from SC QSPI flash into on-chip LIM.
Changes:
- Added M-mode boot path with multi-hart support, L2 cache configuration, and per-hart UART
- Extended HAL with SC QSPI flash driver and UART-based QSPI programmer
- Refactored shared code (SDHCI, SCB mailbox, linker scripts) for both S-mode and M-mode builds
Reviewed changes
Copilot reviewed 19 out of 19 changed files in this pull request and generated 7 comments.
Show a summary per file
| File | Description |
|---|---|
| test-app/vector_riscv.S | Simplified to use mret for M-mode payload |
| test-app/startup_riscv.c | Updated to use M-mode CSRs (mtvec, mcause) |
| test-app/app_mpfs250.c | Removed duplicate UART/HAL init to avoid clearing TX FIFO |
| test-app/RISCV64-mpfs250.ld | Added dummy _main_hart_hls symbol |
| src/vector_riscv.S | Refactored to use MODE_PREFIX macro for CSR access |
| src/update_disk.c | Fixed unused variable warning with conditional compilation |
| src/sdhci.c | Moved power init into card init, added udelay helper, refined debug flags |
| src/boot_riscv_start.S | Added comprehensive M-mode boot sequence with eNVM-to-L2 copy |
| src/boot_riscv.c | Added M-mode to S-mode transition support and direct M-mode jump |
| hal/riscv.h | Extended with CLINT, L2 cache, and additional MSTATUS definitions |
| hal/mpfs250.h | Added L2 cache, UART mapping, HLS structures, and M-mode peripherals |
| hal/mpfs250.c | Refactored with L2 init, multi-hart support, and UART QSPI programmer |
| hal/mpfs250-m.ld | New M-mode linker script for eNVM + L2 SRAM layout |
| docs/Targets.md | Added M-mode documentation and updated S-mode references |
| config/examples/polarfire_mpfs250_m_qspi.config | New M-mode configuration file |
| config/examples/polarfire_mpfs250.config | Updated DTS comment and debug flag name |
| arch.mk | Added M-mode vs S-mode build logic with appropriate flags |
| .github/workflows/test-configs.yml | Added CI tests for M-mode configs |
| .gdbinit | Updated for RISC-V debugging |
💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.
There was a problem hiding this comment.
Pull request overview
Copilot reviewed 20 out of 20 changed files in this pull request and generated 8 comments.
💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.
dgarske
force-pushed
the
polarfire_soc_m
branch
from
c8aa0b5 to
0d5563a
Compare
dgarske
force-pushed
the
polarfire_soc_m
branch
from
0d5563a to
a59bd61
Compare
dgarske
force-pushed
the
polarfire_soc_m
branch
from
a59bd61 to
9b3b7e5
Compare
There was a problem hiding this comment.
Pull request overview
Copilot reviewed 21 out of 21 changed files in this pull request and generated 13 comments.
💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.
There was a problem hiding this comment.
Pull request overview
Copilot reviewed 24 out of 24 changed files in this pull request and generated 13 comments.
💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.
Adds support for running wolfBoot in Machine Mode (M-mode) on the PolarFire SoC MPFS250T, booting from eNVM and loading a signed application from SC QSPI flash into on-chip LIM (Loosely Integrated Memory). No HSS (Hart Software Services) or DDR is required. It also extends the existing PolarFire HAL with multi-hart support, L2 cache configuration, per-hart UART, and refactors shared code (SDHCI, SCB mailbox, linker/test-app) for both S-mode and M-mode builds.